Questions and Answers

Who could use Dauug|18?

Who could use Dauug|36?

How is Dauug|36 more secure than other architectures?

Radical simplicity. On purpose, Dauug|36 has no cache memory, speculative execution, multiprocessing, stack variables, dynamic random-access memory (DRAM), page faults, memory overcommitment, swapping, peripheral direct memory access, nonprivileged indirect jumps, hardware virtualization, or VLSI complex logic. These twelve features are treacherous for even experts to implement, and each is associated with a large family of vulnerabilities. Yet traditional computers tend to have every last one, which is especially reckless for users who don’t need a lot of computing power and uses that don’t require it.

Radical separation. Dauug|36 partitions data, code, and stack memory onto separate chips in separate address spaces. It’s electrically impossible for a code, data, or stack operation to leak into another space. Instruction pointers are isolated from registers and data memory. Stack memory holds return addresses and CPU flags only, never buffers or variables. Every peripheral has its own bus and is unable to reach other devices or memory. Privileged opcodes are trivially distinguishable from nonprivileged. Programs can’t even try to branch outside their own code. It’s electrically impossible for the CPU to read, alter, or update its own firmware. Mainstream computers offer none of these eight guardrails.

Radical ownership. Dauug|36 empowers end users to build their own CPUs, controllers, and minicomputers using only maker-scale assembly tools. All parts can be hand-soldered and remain visually and electrically inspectable after construction. There are no headaches from secret functionality, vendor lock-in, encrypted or closed-source firmware, license fees, use restrictions, copyleft, planned obsolescence, right-to-repair infringements, code signing, nonstandard parts, hidden state, unattributable S-boxes, patents, or VLSI backdoors.

Radical courage. Sometimes the highest right is being right. Today, Dauug|36 is incompatible with every binary executable you’ve heard of, every language compiler, every toolchain. It’s incompatible with Rust’s integer sizes, IEEE 754’s floating point format, ELF executable files, parts of C, some of POSIX, and traditional debuggers. Dauug|36’s entire programming model is different, offering a huge number of registers, no stack pointer, improved integer arithmetic semantics, and a refreshingly capable instruction set. And instead of having the hardware run an operating system as most computers would, Dauug|36 is designed to be run by its operating system—a much safer chain of control.

Do Dauug computers merely dust off 1970s technology?

Not at all. Although Dauug computers resemble 1970s computers in their absence of VLSI complex logic (such as microprocessors, FPGAs, PLDs, and ASICs), their underlying logic family, value proposition, and architectures are completely different. The Dauug architectures use a different logic family for control than they do for computation, and neither of these logic families existed in the 1970s. Control is achieved using Advanced Ultra-low voltage CMOS devices in Texas Instruments’ SN74AUC series. These are extremely fast AND, OR, NOT, NAND, NOR, XOR, and D flip-flop gates that operate on a single bit at a time.

Dauug computers do their computing via a network of fast SRAM ICs that are preloaded with open-source tables (a.k.a. firmware) that define sophisticated operations. As VLSI devices, these SRAM chips do require consideration of potential for bugs and backdoors. They turn out to be mature, generic, standardized, and simple components that happen to contain a lot of repetition. SRAM is an order of magnitude or more simpler than even basic microcontrollers, as evidenced by its datasheets being an order of magnitude or more shorter.

The expressivity of SRAM, which can do any logical operation on 18 or more bits in a single clock cycle, results in an astonishingly sophisticated instruction set. The Dauug|36 arithmetic logic unit, or ALU, permits fully heterogeneous signage for arithmetic. For example, it can directly subtract a 36-bit unsigned number from a signed number, save the result in a signed (or unsigned) register, and remember long after the fact whether the destination was large enough to accurately store the result. The subtraction begins and ends within 4 clock cycles.

Dauug|36’s firmware already implements 190 opcodes, and more are in the pipeline. Their sophistication exceeds what one may naively assume in a CPU that can be assembled from scratch on a kitchen table. For example, counting the number of 1 bits in a 36-bit word (called population count, popcount, or Hamming weight) takes only 8 clock cycles. Any 36-bit permutation can be done in 20 clock cycles. Switching from running one program, to running the operating system kernel, to running a different program, takes 20 clock cycles.

Dauug|36 is named for its 36-bit word size, a byproduct of symmetries characteristic of SRAM ALUs as opposed to held over from vintage systems. SRAM, together with progress in packaging and assembly, are modern additions to economy of construction. It turns out the inflation-adjusted cost for computing power has fallen by a factor of 20,000 since 1970—without needing any microprocessors at all. Dauug computers are an innovation of the 2020s, not the 1970s.

How soon can I own a Dauug|18 or Dauug|36 computer?

The bottleneck is funding. Alpha Dauug estimates that his full attention could have a working, replicable Dauug|18 available for makers within ten months, with Dauug|36 following about a year later. The Dauug House’s total revenues for 2025 were U.S. $446.75, which does not support even a modest stipend for Alpha Dauug’s time. As this level is not tenable in light of the work we have ahead, he is now occupied with fundraising instead of engineering.

The Dauug|36 CPU, memory subsystem, and firmware for about 190 opcodes all work in simulation today. We also have an assembler, real-time operating system (RTOS) kernel named Osmin, our simulation tools, and about 200,000 words of documentation. What’s lacking before a circuit board can be plotted are the I/O subsystem and firmware loader. Our technical path is clear, but our constraint is sponsored time.